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EL7566
Data Sheet May 2, 2003 FN7102.1
Monolithic 6 Amp DC:DC Step-Down Regulator
The EL7566 is a full-feature synchronous 6A step-down regulator capable of up to 96% efficiency. This device operates from 3V to 6V VIN input supply. With internal CMOS power FETs, the device can operate at up to 100% duty ratio, allowing for output voltage range from 0.8V up to nearly VIN.The adjustable high switching frequency of up to 1MHz enables the use of small components, making the whole converter occupy less than 0.9 square inch with components on one side of the PCB. The EL7566 operates at constant frequency PWM mode, making external synchronization possible. The EL7566 features soft-start and full start-up control, which eliminates the in-rush current and enables users to control the start-up of multiple converters to any configuration with ease. The EL7566 also offers a 5% voltage margining capability that allows raising and lowering of the supplies derived from the EL7566 to validate the performance and reliability of system cards quickly and easily during manufacturing testing. A junction temperature indicator conveniently monitors the silicon die temperature, saving designers time in the tedious thermal characterization. The EL7566 is available in a 28-pin HTSSOP package and is specified for operation over the 0C to +85C temperature range.
Features
* Integrated MOSFETs * 6A continuous output current * Up to 96% efficiency * Multiple supply start-up tracking * Built-in 5% voltage margining * 3V to 6V input voltage * 0.9 in2 footprint with components on one side of PCB * Adjustable switching frequency to 1MHz * Oscillator synchronization possible * 100% duty ratio * Junction temperature indicator * Over-temperature protection * Internal soft-start * Variable output voltage down to 0.8V * Power-good indicator * 28-pin HTSSOP package
Applications
* Point-of-regulation power supplies * DSP, CPU Core, and IO supplies * Logic/Bus supplies * Portable equipment
Typical Application Diagram
CC R2 10K R1 21.5K 9100pF 0.047F 3 FB 4 VO 5 VTJ 6 TM 7 SEL 8 LX 2.2H VOUT (2.5V, 6A) 150F 9 LX 10 LX 11 LX 12 LX 13 LX 14 NC STN 26 STP 25 EN 24 PG 23 VDD 22 VIN 21 VIN 20 VIN 19 PGND 18 PGND 17 PGND 16 NC 15 VIN (3V TO 6V) 100F 0.22F RC 10K 2 VREF COSC 27 1 COMP SGND 28 270pF
* DC:DC converter modules
Ordering Information
PART NUMBER EL7566DRE EL7566DRE-T7 EL7566DRE-T13 PACKAGE 28-Pin HTSSOP 28-Pin HTSSOP 28-Pin HTSSOP TAPE & REEL 7" 13" PKG. NO. MDP0048 MDP0048 MDP0048
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL7566
Absolute Maximum Ratings (TA = 25C)
VIN, VDD to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN +0.3V SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V COMP, VREF, FB, VO, VTJ, TM, SEL, PG, EN, STP, STN, COSC to SGND . . . . . -0.3V to VDD +0.3V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +135C Operating Ambient Temperature . . . . . . . . . . . . . . . . . 0C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VIN VREF VREFTC VREFLOAD VRAMP IOSC_CHG IOSC_DIS IVDD IVDD_OFF VDD_OFF VDD_ON TOT THYS ILEAK ILMAX RDSON1 RDSONTC2 RDSONTC ISTP ISTN VPGP VPGN VPG_HI VPG_LO VOVP VFB VFB_LINE GMEA VFB_TC FS IFB Input Voltage Range Reference Accuracy
VDD = VIN = 3.3V, TA = TJ = 25C, COSC = 390pF, Unless Otherwise Specified CONDITIONS MIN 3 1.24 1.26 50 0 < IREF < 50A -1 1.15 0.1V < VOSC < 1.25V 0.1V < VOSC < 1.25V VEN = 1 (L disconnected) EN = 0 2.5 2.8 135 20 EN = 0, LX = 6V (low FET), LX = 0V (high FET) 8 29 25 0.2 VSTP = VIN/2 VSTN = VIN/2 With respect to target output voltage With respect to target output voltage IPG = 1mA IPG = -1mA 10 ILOAD = 0A VIN = 3.3V, VIN = 10%, ILOAD = 0A VCC = 0.65V 0C < TA < 85C, ILOAD = 3A 300 VFB = 0V 85 0.79 0.8 0.2 125 1 370 100 440 200 0.81 0.5 165 6 -14 2.6 0.5 -4 2.5 2.5 4 14 -6 50 10 2 200 8 2.7 1 5 1.5 2.65 2.95 TYP MAX 6 1.28 UNIT V V ppm/C % V A mA mA mA V V C C A A m m m/C A A % % V V % V % s % kHz nA
DESCRIPTION
Reference Temperature Coefficient Reference Load Regulation Oscillator Ramp Amplitude Oscillator Charge Current Oscillator Discharge Current VDD Supply Current VDD Standby Current VDD for Shutdown VDD for Startup Over-temperature Threshold Over-temperature Hysteresis Internal FET Leakage Current Peak Current Limit PFET On Resistance NFET On Resistance RDSON Tempco STP Pin Input Pull-down Current STN Pin Input Pull-up Current Positive Power Good Threshold Negative Power Good Threshold Power Good Drive High Power Good Drive Low Output Over-voltage Protection Output Initial Accuracy Output Line Regulation Error Amplifier Transconductance Output Temperature Stability Switching Frequency Feedback Input Pull-up Current
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EL7566
DC Electrical Specifications
PARAMETER VEN_HI VEN_LO IEN TM, SEL_HI TM, SEL_LO EN Input High Level EN Input Low Level Enable Pull-up Current Input High Level Input Low Level VEN = 0 -4 2.6 1 -2.5 VDD = VIN = 3.3V, TA = TJ = 25C, COSC = 390pF, Unless Otherwise Specified CONDITIONS MIN 2.6 1 TYP MAX UNIT V V A V V
DESCRIPTION
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8, 9, 10, 11, 12, 13 14, 15 16, 17, 18 19, 20, 21 22 23 24 25 26 27 28 PIN NAME COMP VREF FB VO VTJ TM SEL LX NC PGND VIN VDD PG EN STP STN COSC SGND PIN FUNCTION Error amplifier output; place loop compensation components here Bandgap reference bypass capacitor; typically 0.022F to 0.047F to SGND Voltage feedback input; connected to external resistor divider between VOUT and SGND for adjustable output; also used for speed-up capacitor connection Output sense for fixed output; also used for speed-up capacitor connection Junction temperature monitor output Stress test enable; allows 5% output movement; connect to SGND if function is not used Positive or negative stress select; see text Inductor drive pin; high current output whose average voltage equals the regulator output voltage Not used Ground return of the regulator; connected to the source of the low-side synchronous NMOS Power FET Power supply input of the regulator; connected to the drain of the high-side PMOS Power FET Control circuit positive supply; connected to VIN through an internal 20 resistor Power-good window comparator output; logic 1 when regulator output is within 10% of target output voltage Chip enable, active high; a 2A internal pull-up current enables the device if the pin is left open; a capacitor can be added at this pin to delay the start of a converter Auxilliary supply tracking positive input; tied to regulator output to synchronize start-up with a second supply; leave open for standalone operation; 2A internal pull-up current Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start-up; leave open for standalone operation; 2A internal pull-up current Oscillator timing capacitor (see performance curves) Control circuit negative supply or signal ground
3
EL7566 Block Diagram
TM SEL VREF VTJ 2.2nF EN VDD JUNCTION TEMPERATURE VOLTAGE REFERENCE 0.047F COSC 390pF
OSCILLATOR VDD 20 VIN
0.22F VIN 100F 2.2H VOUT (2.5V, 6A) 150F PGND
STP STN
POWER TRACKING PWM CONTROLLER DRIVERS
POWER FET POWER FET
EA CURRENT SENSE COMP RC CC SGND FB R1 R2 VREF + VO VDD PG
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EL7566 Typical Performance Curves
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.2H, CIN = 100F, COUT = 150F, TA = 25C unless otherwise noted.
100 95 EFFICIENCY (%) 90 85 80 75 70 65 60 0 1 2 3 IO (A) 4 5 6 VO=0.8V VO=1V VO=1.2V VO=1.8V VO=3.3V VO=2.5V EFFICIENCY (%)
100 95 90 85 80 75 70 65 60 0 1 2 3 IO (A) 4 5 6 VO=1V VO=1.2V VO=0.8V VO=2.5V VO=1.8V
FIGURE 1. EFFICIENCY (VIN = 5V)
FIGURE 2. EFFICIENCY (VIN = 3.3V)
1.265 1.26 1.255 VTJ VDD=5V 1.25 1.24 1.245 VDD=3.3V
1.6 1.5 1.4
VREF
1.3 1.2 1.1 1 VDD=5V VDD=3.3V
0
50
100
150
0
0
50
100
150
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
FIGURE 3. VREF vs TEMPERATURE
FIGURE 4. VTJ vs TEMPERATURE
4 3.5 3 2.5 2 1.5 1 VEN_LOW VEN_HI FS (kHz)
1200 1000 800 600 500 200 0 100 VDD=3.3V VDD=5V
3
3.5
4
4.5 VDD (V)
5
5.5
6
200
300
400 COSC (pF)
500
600
700
FIGURE 5. VEN_HI & VEN_LOW vs VDD
FIGURE 6. FS vs COSC
5
EL7566 Typical Performance Curves
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.2H, CIN = 100F, COUT = 150F, TA = 25C unless otherwise noted. (Continued)
526 524 SWITCHING FREQUENCY 522 520 518 514 512 510 508 506 504 0 1 2 3 IO (A) 4 5 6 VIN=3.3V (%) 516 VIN=5V
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 0 1 2 3 IO (A) 4 5 6
FIGURE 7. FS vs LOAD CURRENT
FIGURE 8. LOAD REGULATIONS
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD NOT SOLDERED TO PCB
50 45 JA (C/W) 40 35 30 25
POWER DISSIPATION (W)
CONDITION: 28-Pin HTSSOP THERMAL PAD SOLDERED TO 2-LAYER PCB WITH 0.039" THICKNESS AND 1 OZ. COPPER ON BOTH SIDES
1.2 1 0.8 0.6 0.4 0.2 0 1.136W
HT SS =1 OP 2 10 C 8 /W
JA
1
2
3
4
5
6
7
8
9
0
25
50
75 85 100
125
150
PCB AREA (in2)
AMBIENT TEMPERATURE (C)
FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA (NO AIR FLOW)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 4.5 POWER DISSIPATION (W) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 4.167W
JA
HT SS O P2 =3 8 0 C/ W
AMBIENT TEMPERATURE (C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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EL7566 Waveforms
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.2H, CIN = 100F, COUT = 150F, TA = 25C unless otherwise noted.
VIN (5V/DIV) IIN (2A/DIV) VO (2V/DIV)
VIN (200mV/DIV) IL (2A/DIV)
PG
VLX (5V/DIV)
VO (50mV/DIV) 0.5ms/DIV 1s/DIV
FIGURE 12. START-UP
FIGURE 13. STEADY-STATE OPERATION
4.5A VEN IO 1.5A VO (100mV/DIV)
IIN (2A/DIV)
VO (2V/DIV) 50s/DIV
100s/DIV
FIGURE 14. SHUT-DOWN
FIGURE 15. TRANSIENT RESPONSE
TM
PG VO (2V/dIv)
SEL
VO (200mV/DIV)
VLX (5V/DIV)
1ms/DIV
0.5ms/DIV
FIGURE 16. VOLTAGE MARGINING
FIGURE 17. OVER-VOLTAGE SHUT-DOWN
7
EL7566 Waveforms
VIN = VD = 5V, VO = 2.5V, IO = 6A, fS = 500kHz, L = 2.2H, CIN = 100F, COUT = 150F, TA = 25C unless otherwise noted. (Continued)
VIN (5V/DIV) IIN (2A/DIV) VO (2V/DIV)
VIN (5V/DIV)
VO1=2.5V VO2=1.8V
PG
5ms/DIV
5ms/DIV
FIGURE 18. ADJUSTABLE START-UP
FIGURE 19. TRACKING START-UP
Detailed Description
The EL7566 is a full-feature synchronous 6A step-down regulator capable of up to 96% efficiency. This device operates from 3V to 6V VIN input supply. With internal CMOS power FETs, the device can operate at up to 100% duty ratio, allowing for output voltage range from 0.8V up to nearly VIN.The adjustable high switching frequency of up to 1MHz enables the use of small components, making the whole converter occupy less than 0.9 square inch with components on one side of the PCB. The EL7566 operates at constant frequency PWM mode, making external synchronization possible. Patented on-chip resistorless current-sensing enables current mode control, which provides over-current protection, and excellent step load response. The EL7566 features soft-start and full start-up control, which eliminate the in-rush current and enables users to control the start-up of multiple converters to any configuration with ease. The EL7566 also offers a 5% voltage margining capability that allows raising and lowering of the supplies derived from the EL7566 to validate the performance and reliability of system cards quickly and easily during manufacturing testing. A junction temperature indicator conveniently monitors the silicon die temperature, saving designers time in the tedious thermal characterization.
occur. Connecting a small capacitor at EN will delay the start-up. The delay time TD can be calculated by:
V EN_HI T D = C EN x ------------------I EN
where: * CEN is the capacitance at EN pin * VEN_HI is the EN input high level (function of VDD voltage, see Figure 5) * IEN is the EN pin pull-up current, nominal 2.5A If a slower than 2ms soft start-up is needed, please refer to Full Start-Up Control section.
Steady-State Operation
The converter always operates at fixed frequency continuous-conduction mode. For fast transient response, peak current control method is employed. The inductor current is sensed from the upper PFET. This current signal, the slope compensation, and the compensated error signal are fed to the PWM comparator to generate the PWM signal for the internal power switches. When the upper PFET is on, the low-side NFET is off and input voltage charges the inductor. When PFET is off, the NFET is on and energy stored in the inductor is dumped to the output to maintain constant output voltage. Therefore, the LX waveform is always a stable square waveform (see Figure 13) with peak close to VIN. So LX is a good indication that the converter is operating properly.
Start-Up
The EL7566 employs a special soft-start to suppress the inrush current (see Figure 12). The start-up process takes about 2ms and begins when the input voltage reaches about 2.8V and EN pin voltage 2V. When EN is released from LOW, or the converter comes out of thermal shut-down mode, the soft-start process repeats. When the input voltage ramps up too slowly, slight over- current at the input can
100% Duty Ratio
EL7566 uses CMOS as internal synchronous power switches. The upper switch is a PMOS and the lower switch an NMOS. This not only saves a boot capacitor, it also
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EL7566
allows 100% turn-on of the upper PFET switch, achieving VO close to VIN. The maximum achievable VO is:
V O = V IN - ( R L + R DSON1 ) x I O
switching frequency 20% lower than the sync frequency to accommodate component variations.
100pF EL7566 EXTERNAL SYNC SOURCE
Where RL is the DC resistance on the inductor and RDSON1 is the PFET on-resistance, nominal 30m at room temperature with tempco of 0.2m/C.
COSC
Output Voltage Selection
The output voltage can be as high as the input voltage minus the PMOS and inductor voltage drops. Use R1 and R2 to set the output voltage according to the following formula:
R 1 V O = 0.8 x 1 + ------ R 2
FIGURE 20. EXTERNAL SYNC CIRCUIT
Thermal Protection and Junction Temperature Indicator
An internal temperature sensor continuously monitors the junction temperature. In the event that the junction temperature exceeds 135C, the regulator is in a fault condition and will shut down. When the temperature falls back below 110C, the regulator goes through the soft-start procedure again. The VTJ pin is an accurate indicator of the internal silicon junction temperature TJ, which can be determined by the following formula. This saves engineering time.
1.2 - V TJ T J = 75 + -----------------------0.00384
Standard values of R1 and R2 are listed in Table 1.
TABLE 1. VO (V) 0.8 1 1.2 1.5 1.8 2.5 3.3 R1 (K) 2 2.49 4.99 10 12.7 21.5 36 R2 (K) Open 10 10 11.5 10.2 10 11.5
where VTJ is the voltage at the pin.
Under-Voltage Lockout (UVLO)
When VDD falls bellow 2.5V, the regulator shuts down. When VDD rises above 2.8V, converter goes through soft-start process again.
Voltage Margining
The EL7566 has built-in 5% load stress test (commonly called voltage margining) function. Combinations of TM and SEL set the margins shown in Table 2. When this function is not used, both pins should be connected to SGND, either directly or through a 10k resister. Figure 16 shows this feature.
TABLE 2. CONDITION Normal High Margin Low Margin TM 0 1 1 SEL X 1 0 VO Nominal Nominal + 5% Nominal - 5%
Power Good Indicator (PG) and Over-Voltage Protection
When the output reaches 10% of the preset voltage, the PG pin outputs a HI signal as shown in the start-up waveform (Figure 12). If the output voltage is higher than 10% of the preset value for any reason, PG will go low and the regulator will shut down. In addition to the indication power is good, the PG pin can be used for multiple regulators' start-up control as described in the next section.
Full Start-Up Control
The EL7566 offers full start-up control. The core of this control is a start-up comparator in front of the main PWM controller. The STP and STN are the inputs to the comparator, whose HI output forces the PWM comparator to skip switching cycles. The user can choose any of the following control configurations:
Switching Frequency
The regulator operates from 200kHz to 1MHz. The switching frequency is generated by a relaxation comparator and adjusted by a COSC. The triangle waveform has 95% duty ratio and runs from 0.2V to 1.2V. Please refer to Figure 6 for a specific frequency. When external synchronization is required, use the following circuit for connection. Always choose the converter self-
9
EL7566
1. ADJUSTABLE SOFT-START In this configuration, the ramp-up time is adjustable to any time longer than the building soft-start time of 2ms. The approximate ramp-up time, TST, is:
VO T ST = RC --------- V IN
4. OFFSET START-UP Compared with the cascade start-up, this configuration allows Regulator 2 to begin the start-up process when VO1 reaches a particular value of VREF*(1+RB/RA) before PG goes HI, where VREF is the regulator reference voltage. VREF=1.26.
VREF + VO EL7566 STN STP C R 200K VIN TST 0.1F VO VO2
+ VIN
RB RA
EL7566
VO1 EL7566 VIN
VREF(1+RB/RA) VO1 VO2
FIGURE 21. ADJUSTABLE START-UP
2. CASCADE START-UP In this configuration, EN pin of Regulator 2 is connected to the PG pin of Regulator 1 (Figure 22). VO2 will only start after VO1 is good.
FIGURE 24. OFFSET START-UP TRACKING
Component Selection
INPUT CAPACITOR
EN VO2 EL7566 VO1 EL7566 PG VIN
The main functions of the input capacitor(s) are to maintain the input voltage steady and to filter out the pulse current passing through the upper switch. The root-mean-square value of this current is:
V O x ( V IN - V O ) I IN,RMS = ----------------------------------------------- x I O 1/2 ( I O ) V IN
VO1 VO2
for a wide range of VIN and VO.
FIGURE 22. CASCADE START-UP
3. LINEAR START-UP In the linear start-up tracking configuration, the regulator with lower output voltage, VO2, tracks the one with higher output voltage, VO1.
For long-term reliability, the input capacitor or combination of capacitors must have the current rating higher than IIN,RMS. Use X5R or X7R type ceramic capacitors, or SPCAP or POSCAP types of Polymer capacitors for their high current handling capability. INDUCTOR The NFET positive current limit is set at about 0.8A. For optimal operation, the peak-to-peak inductor current ripple IL should be less than 1.5A. The following equation gives the inductance value:
( V IN - V O ) x V O L = ------------------------------------------V IN x I L x F S
+ VO2 EL7566 VO1 VIN
+
STN STP
C
R VIN
EL7566
VO1 VO2
The peak current the inductor sees is:
I L I LPK = I O + -------2
FIGURE 23. LINEAR START-UP TRACKING
When inductor is chosen, make sure the inductor can handle this peak current and the average current of IO.
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EL7566
OUTPUT CAPACITOR If there is no holding time requirement for output; output voltage ripple and transient response are the main deciding factors in choosing the output capacitor. Initially, choose the output capacitor with the ESR to satisfy the output ripple VO requirement:
V O = I L x ESR
Design Example A 5V to 2.5V converter at 6A is needed. 1. Choose the input capacitor The input capacitor or combination of capacitors has to be able to take about 1/2 of the output current, e.g., 3A. Panasonic EEFUD0J101XR is rated at 3.3A, 6.3V, meeting the above criteria. 2. Choose the inductor. Set the converter switching frequency at 500kHz:
( V IN - V O ) x V O L = ------------------------------------------V IN x I L x F S
When output has a step load change IO, the initial voltage drop is ESR*IO. Then VO will drop even further before the loop has the chance to respond. The higher the output capacitance, the lower the voltage drop is. Also, higher loop bandwidth will generate less voltage drop. Experiment with the transient response (see Figure 15) to determine the final values of output capacitance. Like the input capacitor, it is recommended to use X5R or X7R type of ceramic capacitors, or SPCAP or POSCAP type of Polymer capacitors for the low ESR and high capacitance. Generally, the AC current rating of the output capacitor is not a concern because the RMS current is only 1/8 of IL. This is easily satisfied. LOOP COMPENSATION Current mode converter forces the inductor current proportional to the error signal, thus gets rid of the 2nd order effect formed by the inductor and output capacitor. The PWM comparator and the inductor form an equivalent transconductance amplifier. So, a simple Type 1 compensator is good enough to generate a high bandwidth stable converter. The compensation resister is decided by:
F C x 2 x x ( ESR + R OUT ) x C OUT IO R C = ----------- x ------------------------------------------------------------------------------------------------VFB GM PWM x GM EA
IL = 1.5A yields 1.6H. Leave some margin and choose L = 2.2H. Coilcraft's DO3316P-222HC has the required current rating. 3. Choose the output capacitor L = 2.2H yields about 1A inductor ripple current. If 25mV of ripple is desired, COUT's ESR needs to be less than 25m. Panasonic's EEFUD0G151XR 150F has ESR of 12m and rated at 4V. ESR is not the only factor deciding the output capacitance. As discussed earlier, output voltage droops less with more capacitance when converter is in load transient. Multiple iterations may be needed before final components are chosen. 4. Loop compensation 50kHz is the intended crossover frequency. With the conditions RC and CC are calculated as: RC = 10.5k and CC = 8900pF, round to standard value of 8200pF. For convenience, Table 3 lists the compensation values for frequently used output voltages.
TABLE 3. COMPENSATION VALUES VO (V) 3.3 2.5 1.8 1.5 1.2 1 0.8 RC (K) 13.7 10.5 7.68 6.49 5.23 4.42 3.57 CC (PF) 8200 8200 8200 8200 8200 8200 8200
where: * GMPWM is the transconductance of the PWM comparator, GMPWM = 120S
VO R OUT = ------IO
* ESR is the ESR of the output capacitor * COUT is output capacitance * GMEA is the transconductance of the error amplifier, GMEA = 120S * FC is the intended crossover frequency of the loop. For best performance, set this value to about one-tenth of the switching frequency. * Once RC is chosen, CC is decided by:
R OUT C C = 1.5 x C OUT x --------------RC
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EL7566
Thermal Management
The EL7566DRE is packaged in a thermally-efficient HTSSOP-28 package, which utilizes the exposed thermal pad at the bottom to spread heat through PCB metal. Therefore: 1. The thermal pad must be soldered to the PCB 2. Maximize the PCB area 3. If a multiple layer PCB is used, thermal vias (13 to 25 mil) must be placed underneath the thermal pad to connect to ground plane(s). Do not place thermal reliefs on the vias. Figure 25 shows a typical connection. The thermal resistance for this package is as low as 26C/W for 2 layer PCB of 0.39" thickness (see Figure 9). The actual junction temperature can be measured at VTJ pin. The thermal performance of the IC is heavily dependent on the layout of the PCB. The user should exercise care during the design phase to ensure the IC will operate within the recommended environmental conditions.
Layout Considerations
The layout is very important for the converter to function properly. Follow these tips for best performance: 1. Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the SGND pin 2. Place the input capacitor(s) as close to VIN and PGND pins as possible 3. Make as small as possible the loop from LX pins to L to CO to PGND pins 4. Place R1 and R2 pins as close to the FB pin as possible 5. Maximize the copper area around the PGND pins; do not place thermal relief around them 6. Thermal pad should be soldered to PCB. Place several via holes under the chip to the ground plane to help heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7566 Application Brief.
COMPONENT SIDE CONNECTION
GROUND PLANE CONNECTION
FIGURE 25. PCB LAYOUT - 28-PIN HTSSOP PACKAGE
12
EL7566 Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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